Memory arrays, which store large amounts of data, are known in the art. Over the years, manufacturers and designers have worked to make the arrays physically smaller but the amount of data stored therein larger.
Computing devices typically have one or more memory array to store data and a central processing unit (CPU) and other hardware to process the data. The CPU is typically connected to the memory array via a bus. Unfortunately, while CPU speeds have increased tremendously in recent years, the bus speeds have not increased at an equal pace. Accordingly, the bus connection acts as a bottleneck to increased speed of operation.
U.S. Pat. No. 8,238,173 to Akerib et at. and assigned to the common assignee of the present invention discloses a processor which may perform in-memory computations. The processor includes a memory array to store data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time to generate a Boolean function output of the data of the at least two cells. The Boolean function output may then be stored inside the memory array for further processing, including to generate new Boolean function outputs. This operation may be repeated numerous times until the desired results are achieved. The results may then be output for further use. Also disclosed therein is a content addressable memory (CAM) unit, including a ternary CAM (T-CAM) unit which may he implemented using the principles of operation of the in-memory processor.